#include "test_main.h"

uint32_t count=0;
uint32_t count1=0;


int main(void) {
  clock_init();
  SystemCoreClockUpdate();
	WRITE_REG((*(__IO uint32_t *) 0x40002024),0x05); //	NVR&PARA LOCK		
  gpio_init();
	
	//INITIAL TMR bias voltage
	WRITE_REG(MISC->TMR_DAC_VB_REG,0x00030C30); 		//set  TMR bias voltage 2.05V
	
	
	
 /*ram_init*/
	uint32_t base_addr = 0x20000100;
	uint16_t i;
  for (i=0; i<64; i++) {
    *(uint32_t *)base_addr =0;
    base_addr = base_addr + 4;
  }	
	
	DrvAdcInit();//ADC init
	WRITE_REG(ADC->DMA_INT_CR,0x80007000);//enable sq_tr_dma,Update ADC data every time scanning has been finished
	WRITE_REG (ADC->INT_CLR,0x1);// CLEAR adc int
  WRITE_REG (*(__IO uint32_t *)0x400111B8, 0x0000001F);//clear DMA_INT_ST 

	//dma_ram2spi2tx_init();
	WRITE_REG(DMA_CH0->RD_START_ADDR, 0x40011ff0);//read adress
  WRITE_REG(DMA_CH0->WR_START_ADDR, 0x20000100);//write adress
  WRITE_REG(DMA_CH0->BLOCK_SIZE, 0x00000020);//Set DMA Block Size
  WRITE_REG(DMA_CH0->CMD_REG, 0x00000003);
  WRITE_REG(DMA_CH0->STATIC0_REG, 0x00000004);  //read 4 byte pre times
  WRITE_REG(DMA_CH0->STATIC1_REG, 0x80000004);  //write 4 byte pre times
  WRITE_REG(DMA_CH0->STATIC2_REG, 0x00000000);  //
  WRITE_REG(DMA_CH0->PERIPHCTL, 0x00000708);//RD_PERIPH_NUM=8,RD_PERIPH_DELAY=2,WR_PERIPH_NUM=0,WR_PERIPH_DELAY=6
  WRITE_REG(DMA_CH0->INT_ENABLE_REG, 0x00000001);//
	WRITE_REG(DMA_CH0->ENABLE_REG, 0x00000001);//enable DMA_CH0
	NVIC_EnableIRQ(kDmaCh1Irqn);
	
	count1=0;
	
	//piezo init and start
	DrvPiezo_Init();
	
	DrvAdcStart();//start adc
	DrvDMAChannelEnable(DMA_CH0);//Enable DMA_CH0
	WRITE_REG(*(__IO uint32_t *)0x40001044, 0x00000001);//START dma_ch0

while (1) {
		count1++;

}
}

void DMA_CH0_IRQHandler (void) { 
if(READ_BIT(DMA_CH0->STATUS_REG, DMA_INT_STATUS_REG_INT_STATUS_CH_END)) {
	WRITE_REG(*(__IO uint32_t *)0x400010A4, 0xFF);
		if(count>256){
			NVIC_DisableIRQ(kDmaCh1Irqn);
			DrvDMAChannelDisable(DMA_CH0);
		}
		else{
		count+=32;
		DrvDMAConfigAddress(DMA_CH0, 0x40011FF0, 0x20000100+count);
		WRITE_REG(*(__IO uint32_t *)0x40001044, 0x00000001);//START dma_ch0
		}
		
    }
  }
	
